The present invention relates to the field of programmable logic integrated circuits. More specifically, the present invention provides an enhanced programmable logic architecture, improving upon the composition, configuration, and arrangements of logic array blocks and logic elements and also the interconnections between these logic array blocks and logic elements.
Programmable Logic Devices (PLDs) are well known to those in the electronic art. Such programmable logic devices are commonly referred as PALs (Programmable Array Logic), PLAs (Programmable Logic Arrays), FPLAs (Field Programmable Logic Arrays), PLDs (Programmable Logic Devices), EPLDs (Erasable Programmable Logic Devices), EEPLDs (Electrically Erasable Programmable Logic Devices), LCAs (Logic Cell Arrays), FPGAs (Field Programmable Gate Arrays), and the like. Such devices are used in a wide array of applications where it is desirable to program standard, off-the-shelf devices for a specific application. Such devices include, for example, the well-known, Classic.TM., MAX.RTM. 5000, MAX.RTM. 7000, FLEX.RTM. 8000, and FLEX.RTM. 10K families of devices made by Altera Corp.
PLDs are generally known in which many logic array blocks (LABs) are provided in a two-dimensional array. Further, PLDs have an array of intersecting signal conductors for programmably selecting and conducting logic signals to, from, and between the logic array blocks. LABs contain a number of relatively elementary logic individual programmable logic elements (LEs) which provide relatively elementary logic gates such as NAND, NOR, and exclusive OR gates.
Resulting from the continued scaling and shrinking of semiconductor device geometries, which are used to form integrated circuits (also known as "chips"), integrated circuits have progressively become smaller and denser. For programmable logic, it becomes possible to put greater numbers of programmable logic elements onto one integrated circuit. Furthermore, as the number of elements increases, it becomes increasingly important to improve the techniques and architectures used for interconnecting the elements and routing signals between the logic blocks. In particular, it is important to provide enough interconnection resources between the programmable logic elements so that the capabilities of the logical elements can be fully utilized and so that complex logic functions (e.g., requiring the combination of multiple LABs and LEs) can be performed, without providing so much interconnection resources that there is a wasteful excess of this type of resource.
While such devices have met with substantial success, such devices also meet with certain limitations, especially in situations in which the provision of additional or alternative types of interconnections between the logic modules would have benefits sufficient to justify the additional circuitry and programming complexity. Such additional interconnection paths may be desirable for making frequently needed kinds of interconnections, for speeding certain kinds of interconnections, for allowing short distance connections to be made without tying up more general purpose and therefore long distance interconnection resources, etc. There is also a continuing demand for logic devices with larger capacity. This produces a need to implement logic functions more efficiently and to make better use of the portion of the device which is devoted to interconnecting individual logic modules.
As can be seen, an improved programmable logic array integrated circuit architecture is needed, especially an architecture providing additional possibilities for interconnections between the logic modules and improved techniques for organizing and interconnecting the programmable logic elements, including LABs and LEs.
The present invention relates generally to the field of integrated circuits and their operation. More specifically, in one embodiment, the invention provides an improved logic device and method of its operation.
Logic devices and their methods of operation are well known to those of skill in the art. In particular, programmable logic devices have found wide application as a result of their combined low up front cost and versatility to the user.
Altera's FLEX.RTM. and MAX.RTM. lines of programmable logic devices are among the most advanced and successful programmable logic devices in the industry. In the FLEX.RTM. logic devices, a large matrix of logic elements is utilized. In a current commercial embodiment of such devices, each logic element includes a 4-input look-up table for performance of combinational logic and a register that provides for synchronous logic operation.
The logic elements are arranged in groups of, for example, eight logic elements to form larger logic array blocks (LABs). The LABs contain, among other things, a local interconnection structure. The local interconnections allow the outputs of the logic elements to be efficiently routed to other logic elements within a LAB. The various LABs are arranged on the device in a two dimensional array. The various LABs may be connected to each other and to pins of the device though continuous lines that run the entire length and width of the device.
The FLEX.RTM. logic devices have met with substantial success and are considered pioneering in the area of programmable logic. While pioneering in the industry, certain limitations still remain. For example, it would be desirable to further increase the flexibility of the user and CAD software to program the device. In the presently available configurations, a particular signal may be blocked. That is, the signal cannot be routed out of an logic element or LAB because a path is not available. It is desirable to create a configuration in which blocked signals are minimized.
From the above, it is apparent that an improved logic device and method of its operation is desirable.